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Pré-Publication, Document De Travail Année : 2021

Hardware-aware Design of Multiplierless Second-Order IIR Filters with Minimum Adders

Résumé

In this work, we optimally solve the problem of multiplierless design of second-order Infinite Impulse Response filters with minimum number of adders. Given a frequency specification, we design a stable direct form filter with hardware-aware fixed-point coefficients that yielding minimal number of adders when replacing all the multiplications by bit shifts and additions. The coefficient design, quantization and imple- mentation, typically conducted independently, are now gathered into one global optimization problem, modeled through integer linear programming and efficiently solved using generic solvers. We guarantee the frequency-domain specifications and stability, which together with optimal number of adders will significantly simplify design-space exploration for filter designers. The optimal filters are implemented within the FloPoCo IP core generator and synthesized for Field Programmable Gate Arrays. With respect to state-of-the-art three-step filter design methods, our one-step design approach achieves, on average, 42% reduction in number of lookup tables and 21% improvement in delay.
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Dates et versions

hal-03208221 , version 1 (26-04-2021)
hal-03208221 , version 2 (04-08-2021)
hal-03208221 , version 3 (14-01-2022)

Identifiants

  • HAL Id : hal-03208221 , version 2

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Rémi Garcia, Anastasia Volkova, Martin Kumm, Alexandre Goldsztejn, Jonas Kühle. Hardware-aware Design of Multiplierless Second-Order IIR Filters with Minimum Adders. 2021. ⟨hal-03208221v2⟩
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